vishay siliconix si1022r document number: 71331 s10-2687-rev. f, 22-nov-10 www.vishay.com 1 n-channel 60 v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 definition ?trenchfet ? power mosfets ? low on-resistance: 1.25 ? ? low threshold: 2.5 v ? low input capacitance: 30 pf ? fast switching speed: 25 ns ? low input and output leakage ? miniature package ? esd protected: 2000 v ? compliant to rohs directive 2002/95/ec applications ? drivers: relays, solenoids, lamps, hammers, displays, memories, transistors, etc. ? battery operated systems ? solid state relays benefits ? low offset voltage ? low-voltage operation ? high-speed circuits ? low error voltage ? small board area product summary v ds(min.) (v) r ds(on) ( ? )v gs(th) (v) i d (ma) 60 1.25 at v gs = 10 v 1 to 2.5 330 notes: a. surface mounted on fr4 board, power applied for t ? 10 s. markin g code: e sc-75a (sot-416) 1 2 3 g s d orderin g information: si1022r-t1-ge3 (lead (p b )-free and halogen-free) absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 60 v gate-source voltage v gs 20 continuous drain current a t a = 25 c i d 330 ma t a = 85 c 240 pulsed drain current a i dm 650 power dissipation a t a = 25 c p d 250 mw t a = 85 c 130 thermal resistance, maximum junction-to-ambient a r thja 500 c/w operating junction and storage temperature range t j , t stg - 55 to 150 c
www.vishay.com 2 document number: 71331 s10-2687-rev. f, 22-nov-10 vishay siliconix si1022r notes: a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. for design aid only, not subject to production testing. c. switching time is essentially independent of operating temperature. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 10 a 60 v gate-threshold voltage v gs(th) v ds = v gs , i d = 0.25 ma 12.5 gate-body leakage i gss v ds = 0 v, v gs = 10 v 150 na t j = 85 c 500 v ds = 0 v, v gs = 5 v 20 zero gate voltage drain current i dss v ds = 50 v, v gs = 0 v 10 t j = 85 c 100 v ds = 60 v, v gs = 0 v 1a on-state drain current a i d(on) v ds = 10 v, v gs = 4.5 v 500 ma v ds = 7.5 v, v gs = 10 v 800 drain-source on-state resistance a r ds(on) v gs = 4.5 v, i d = 200 ma 3.0 ? t j = 125 c 5.0 v gs = 10 v, i d = 500 ma 1.25 t j = 125 c 2.25 forward transconductance a g fs v ds = 10 v, i d = 200 ma 100 ms diode forward voltage a v sd v gs = 0 v, i s = 200 ma 1.3 v dynamic b input capacitance c iss v ds = 25 v, v gs = 0 v, f = 1 mhz 30 pf output capacitance c oss 6 reverse transfer capacitance c rss 2.5 gate charge q g v ds = 10 v, i d = 250 ma, v gs = 4.5 v 0.6 nc switching b, c tu r n - o n t i m e t (on) v dd = 30 v, r l = 150 ? , i d = 200 ma, v gen = 10 v, r g = 10 ? 25 ns turn-off time t (off) 35
document number: 71331 s10-2687-rev. f, 22-nov-10 www.vishay.com 3 vishay siliconix si1022r typical characteristics (t a = 25 c, unless otherwise noted) output characteristics on-resistance vs. drain current gate charge 0.0 0.2 0.4 0.6 0. 8 1.0 012345 v ds - drain-to-so u rce v oltage ( v ) - drain c u rrent (a) i d v gs = 10 v thr u 7 v 3 v 5 v 4 v 6 v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 200 400 600 8 00 1000 i d - drain c u rrent (ma) v gs = 4.5 v v gs = 10 v - on-resistance ( ) r ds(on) 0 1 2 3 4 5 6 7 0.0 0.1 0.2 0.3 0.4 0.5 0.6 v ds = 10 v i d = 250 ma - gate-to-so u rce v oltage ( v ) q g - total gate charge (nc) v gs transfer characteristics capacitance on-resistance vs. junction temperature 0 300 600 900 1200 0123456 v gs - gate-to-so u rce v oltage ( v ) - drain c u rrent (ma) i d t j = - 55 c 125 c 25 c 0 10 20 30 40 50 0510152025 v ds - drain-to-so u rce v oltage ( v ) c - capacitance (pf) c rss c oss c iss v gs = 0 v f = 1 mhz 0.0 0.4 0. 8 1.2 1.6 2.0 - 50 - 25 0 25 50 75 100 125 150 t j - j u nction temperat u re (c) v gs = 10 v at 500 ma v gs = 4.5 v at 200 ma ( n ormalized) - on-resistance r ds(on)
www.vishay.com 4 document number: 71331 s10-2687-rev. f, 22-nov-10 vishay siliconix si1022r typical characteristics (t a = 25 c, unless otherwise noted) vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71331 . source-drain diode forward voltage threshold voltage variance over temperature 1.2 1.5 1 100 1000 0 0.3 0.6 0.9 t j = 25 c t j = 125 c v sd - so u rce-to-drain v oltage ( v ) - so u rce c u rrent (a) i s 10 t j = - 55 c v gs = 0 v v ariance ( v ) v gs(th) -0. 8 - 0.6 - 0.4 - 0.2 0.0 0.2 0.4 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a t j - j u nction temperat u re (c) on-resistance vs. gate-source voltage single pulse power, junction-to-ambient 0 1 2 3 4 5 0246 8 10 v gs - gate-to-so u rce v oltage ( v ) i d = 500 ma i d = 200 ma - on-resistance ( ) r ds(on) 0.01 0 1 2.5 3 100 600 0.1 po w er ( w ) time (s) 1.5 2 0.5 1 10 t a = 25 c normalized thermal transient impedance, junction-to-ambient 10 -3 10 -2 0 0 6 0 1 1 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1. d u ty cycle, d = 2. per unit base = r thja = 500 c/ w 3. t jm - t a = p dm z thja (t) t 1 t 2 t 1 t 2 n otes: 4. s u rface mo u nted p dm
package information www.vishay.com vishay siliconix revision: 08-aug-11 1 document number: 71348 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 sc-75a: 3-leads notes dimensions in millimeters will govern. 1. dimension d does not include mold flash, protrusions or gate burrs. mold flash protrusions or gate burrs shall not exceed 0.10 mm per end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.10 mm per side. 2. dimensions d and e1 are determi ned at the outmost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interelead flash, but includi ng any mismatch between the top and bottom of the plastic body. 3. datums a, b and d to be determined 0.10 mm from the lead tip. 4. terminal positions are shown for reference only. 5. these dimensions apply to the flat section of the lead between 0.08 mm and 0.15 mm from the lead tip. c m b a ? 2x 1 2 3 a 1 2 d c bbb 4 b 3 d 3 d d d bbb d bbb d e2 b1( b 1) 3 e1 2xb1 e1 2x e3 2 e e/2 d bbb 4x d seating plane a a2 a1 base metal with tin planting section b-b 5 b1 b 1 c c1 l2 l l1 b b 2x 1 ddd c c 1 1 dimensions tolerances aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.10 millimeters dim. min. nom. max. note a- -0.80 a 1 0.00 - 0.10 a 2 0.65 0.70 0.80 b 1 0.19 - 0.24 5 b 1 0.17 - 0.21 c 0.13 - 0.15 5 c 1 0.10 - 0.12 5 d 1.48 1.575 1.68 1, 2 e 1.50 1.60 1.70 e 1 0.66 0.76 0.86 1, 2 e 1 0.50 bsc e 2 1.00 bsc e 3 0.50 bsc l 0.15 0.205 0.30 l 1 0.40 ref l 2 0.15 bsc ? 0 - 8 ? 1 4 - 10 ecn: e11-2210-rev. d, 08-aug-11 d w g: 5868
application note 826 vishay siliconix document number: 72603 www.vishay.com revision: 21-jan-08 19 application note recommended minimum pads for sc-75a: 3-lead 0.014 (0.356) 0.071 (1.803) recommended mi nimum pads dimensions in inches/(mm) 0.264 (0.660) 0.054 (1.372) 0.031 (0.798) 0.020 (0.503) return to index return to index
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